Microprocessors exist that implement a reduced instruction set computing (RISC) instruction set architecture (ISA) and an independent complex instruction set computing (CISC) ISA by emulating the CISC instruction with instructions native to the RISC instruction set. Instructions from the CISC ISA are called “macroinstructions.” Instructions from the RISC ISA are called “microinstructions.” Existing microprocessors do not implement these two architectures as efficiently as can be done. Some existing processors use more global wires routing data to many parts of the chip. This makes chip routing more difficult and less efficient. These techniques also complicate the timing and the pipeline of the processor. It is desirable to create an efficient means of implementing both architectures on a single chip, while leveraging existing hardware. In particular, it is desirable to localize processing and dispatching of the instructions, with minimal impact on the existing execution engine.